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Low contact resistance and dense assembly towards high drive current carbon nanotube transistors

Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of VLSI circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon nanotubes. Furthermore, low-temperature fabrication (e.g. < 400°C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a memory and logic device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, limitations to both the characteristics of the CNT materials and the transistor components must be overcome to realize these transformative benefits. Existing techniques that yield functional CNT transistors without achieving high drive current will not be sufficient. Furthermore, real-world applications in very-large-scale-integration require demonstrations that scale to large substrate area and are supported by statistically significant measurements. This thesis aims to develop, demonstrate, and describe a set of process techniques and fabrication sequences that could enable a robust high drive current CNT technology within existing CMOS manufacturing infrastructure. First, I demonstrate a deposition method for solution-dispersed CNTs that achieves many of the desired characteristics for high drive current transistors. Characterization reveals a CNT density of 150-200 CNT/µm within the aligned region and a CNT alignment standard deviation of +/- 15°. Due to the improved alignment and density there is an average of 45× higher drive current compared to random network deposited CNTs for 1 µm channel length CNFETs. I demonstrate the scalability of this approach to full wafer size. These results motivated efforts to overcome key challenges with existing processes including 1) low current per CNT due to small diameter semiconducting CNTs, 2) CNT bundling due to solution-purified CNT assembly, and 3) high contact resistance due to Schottky barriers at the metal-CNT interface. Next, to overcome the limitations of small diameter CNTs and enable high drive current CNFETs, I evaluated the effectiveness of polymer sorting methods for purifying large diameter semiconducting CNTs. In collaboration with researchers developing novel large-backbone polymer CNT sorting methods, I demonstrate and iteratively refine methods to achieve effective sorting of large 1.2-1.7 nm diameter arc discharge CNTs. Using electrical measurements on short-channel CNFETs I quantified the semiconducting purity to a high degree of statistical confidence. Initial results achieved 99.6% and 99.7% pure semiconducting using large-backbone polymers. Combining the large-backbone polymer sorting with reduced temperature step to enhance the CNT aggregation resulted in detection of as little as 1 metallic CNT in a population of 35,000 CNTs. This is the best reported purity to-date that meets the technology targets with 99.997% concentration semiconducting CNT. To achieve high density CNTs that are aligned, wafer-scale, low cost, and clean defect-free I systematically investigated new approaches to increase the wafer-scale density of aligned CNTs grown by catalytic chemical vapor deposition. These efforts yielded two key advances: 1) I demonstrated record high density 15-21 CNT/µm growth of aligned CNTs at a 100 mm wafer-scale verified by large statistical datasets of CNT-CNT spacing across the wafer. Combined with existing multiple transfer methods this may enable a path to achieve the highest end of the technology density targets of 200 CNT/µm; and 2) I develop new understanding of the mechanisms and process window that enable high density aligned CNT growth. Specifically, the large sensitivity between the catalyst film thickness near the high-density condition is revealed and reproduced at the wafer-scale. Additionally, the effects of growth temperature, H2 concentration, carbon source flow, and reduction condition are systematically studied to identify an optimal process window for high density aligned CNTs. High contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance in series with the channel resistance reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains un-studied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. I investigated by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact length. These CNFET contacts are ≈15 nm shorter than the state-of-the-art Si CMOS "7 nm node" contact length allowing for multiple generations of future scaling of the transistor contacted gate pitch. For 10 nm contacts I reported record-low contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at VDS = 0.7 V compared to the best reported 200 nm contacts to-date. An analysis of contact resistance (RC) from 232 single-CNT CNFETs between the long contact (e.g. 200 nm) and short-contact (e.g. 10 nm) regimes quantified the resistance variation and projects the impact on CNFET current variability versus number of CNT in the transistor. The resistance distribution revealed contact length dependent RC variations become significant below 20 nm contact length. However, a larger source of CNFET resistance variation is apparent at all contact lengths used in this work. To further investigate the origins of this contact length independent resistance variation I analyzed variation of RC in arrays of identical CNFETs along a single CNT of constant diameter and observed random occurrence of high RC even on correlated CNFETs.